SystemVerilog

SystemVerilog, standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a hardware description and hardware verification language commonly used to model, design, simulate, test and implement electronic systems in the semiconductor and electronic design industry. SystemVerilog is an extension of Verilog. Wikipedia

Created Year: 2002
Designed by: Institute of Electrical and Electronics Engineers
File extensions: sv, svr

Wikidata: Q1387402

Programming paradigms: structured programming • object-oriented programming

Language types: hardware description language • hardware verification language