SystemVerilog

SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008, Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog. Wikipedia

Created Year: 2002
Designed by: Institute of Electrical and Electronics Engineers
File extensions: sv, svr

Wikidata: Q1387402

Programming paradigms: object-oriented programming • structured programming

Language types: hardware description language • hardware verification language